Several trends exist today in the semiconductor device fabrication industry and the electronics industry. Devices are continuously getting smaller and requiring less power. A reason for this is that more personal devices are being fabricated that are relatively small and portable, thereby relying on a small battery as its supply source. For example, cellular phones, personal computing devices, and personal sound systems, personal digital assistants, and the like are devices that are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are requiring more computational power and on-chip memory. In light of these trends and others, there is a need in the industry to provide devices that have a relatively large amount of memory. Additionally, it is also desirable that the memory maintains its information with or without power. Memory that retains its contents while a signal is not continuously applied to it is called a non-volatile memory. Examples of conventional non-volatile memory include: electrically erasable, programmable read only memory (“EEPROM”) and FLASH EEPROM.
A ferroelectric memory (FRAM) is a non-volatile memory that utilizes a ferroelectric material as the capacitor dielectric situated between a bottom electrode and a top electrode. Both read and write operations are performed for a FRAM. The memory size and memory architecture affect the read and write access times of a FRAM. Table 1 illustrates exemplary differences between different memory types.
TABLE 1FRAMPropertySRAMFlashDRAM(Demo)Voltage>0.5 VRead >0.5 V>1 V>1 VWrite (12 V)(±6 V)Special TransistorsNOYESYESNO(High Voltage)(LowLeakage)Write Time<10 ns100 ms<30 ns<50 nsWrite EnduranceNA<105NA>1013Read Time (single/<10 ns<30 ns<30 ns/<2<50 nsmulti bit)nsRead EnduranceNA>1015NA>1013Added Mask for0~6–8~6–8~2embeddedCell Size (F~metal~80 F2~8 F2~8 F2~18 F2pitch/2)ArchitectureNDRONDRODRODRONon volatileNOYESNOYESStorageIQ chargeQ chargePcurrentpolarization
The non-volatility of an FRAM is due to the bi-stable characteristic of the ferroelectric memory cell. Two types of memory cells are typically used, a single capacitor memory cell and a dual capacitor memory cell. The single capacitor memory cell (referred to as a 1T/1C memory cell) requires less silicon area (thereby increasing the potential density of the memory array), but is less immune to noise and process variations. Additionally, a 1T/1C cell requires a voltage reference for determining a stored memory state. The dual capacitor memory cell (referred to as a 2T/2C memory cell) requires more silicon area, and it stores complementary signals allowing differential sampling of the stored information. The 2T/2C memory cell has relatively more signal margin than a 1T/1C memory cell.
As illustrated in prior art FIG. 1, a 1T/1C FRAM cell 10 includes one transistor 12 and one ferroelectric storage capacitor 14. A bottom electrode of the storage capacitor 14 is connected to a drain terminal 15 of the transistor 12. The 1T/1C cell 10 is read by applying a signal to the gate 16 of the transistor (word line WL) (e.g., the Y signal), thereby connecting the bottom electrode of the capacitor 14 to the source of the transistor (the bit line BL) 18. A pulse signal is then applied to the top electrode contact (the plate line or drive line DL) 20. The potential on the bit line 18 of the transistor 12 is, therefore, the capacitor charge divided by the bit line capacitance. Since the capacitor charge is dependent upon the bi-stable polarization state of the ferroelectric material, the bit line potential can have two distinct values. A sense amplifier (not shown) is connected to the bit line 18 and detects the voltage associated with a logic value of either 1 or 0. The sense amplifier reference voltage is generated by a ferroelectric or non-ferroelectric capacitor connected to complement bit line that is being read. In this manner, the memory cell data is retrieved.
A characteristic of the shown ferroelectric memory cell is that a read operation is destructive. The data in a memory cell is then rewritten back to the memory cell after the read operation is completed. This is analogues to the operation of a DRAM. One difference from a DRAM is that a ferroelectric memory cell will retain its state until it is interrogated, thereby eliminating the need of refresh.
As illustrated, for example, in prior art FIG. 2, a 2T/2C memory cell 30 in a memory array couples to a bit line 32 and an inverse of the bit line (“bit line-bar”) 34 that is common to many other memory types (for example, static random access memories). Memory cells of a memory block are formed in memory rows and memory columns. The dual capacitor ferroelectric memory cell comprises two transistors 36 and 38 and two ferroelectric capacitors 40 and 42, respectively. The first transistor 36 couples between the bit line 32 and a first capacitor 40, and the second transistor 38 couples between the bit line-bar 34 and the second capacitor 42. The first and second capacitors 40 and 42 have a common terminal or plate (the drive line DL) 44 to which a signal is applied for polarizing the capacitors.
In a write operation, the first and second transistors 36 and 38 of the dual capacitor ferroelectric memory cell 30 are enabled (e.g., via their respective word line 46) to couple the capacitors 40 and 42 to the complementary logic levels on the bit line 32 and the bit line-bar 34 corresponding to a logic state to be stored in memory. The common terminal 44 of the capacitors is pulsed during a write operation to polarize the dual capacitor memory cell 30 to one of the two logic states.
In a read operation, the first and second transistors 36 and 38 of the dual capacitor memory cell 30 are enabled via the word line 46 to couple the information stored on the first and second capacitors 40 and 42 to the bar 32 and the bit line-bar 34, respectively. A differential signal (not shown) is thus generated across the bit line 32 and the bit line-bar 34 by the dual capacitor memory cell 30. The differential signal is sensed by a sense amplifier (not shown) that provides a signal corresponding to the logic level stored in memory.
As stated above, a ferroelectric capacitor includes a ferroelectric layer as a dielectric material sandwiched between a bottom electrode and a top electrode. The various read/write operations described supra utilize the ferroelectric properties, polarization, of the ferroelectric layer. However, over time, the ferroelectric properties of the ferroelectric capacitor can alter.
Data retention is the ability of a memory cell, particularly a non-volatile memory cell, to properly maintain stored data. Proper operation, including data retention, of ferroelectric memory devices depends on the bi-stable characteristic of the ferroelectric memory cell described above. However, over time, the bi-stable characteristic can degrade significantly and negatively affect data retention. Thus, ferroelectric memory devices can, over time, become unusable for some applications. Testing and characterization of ferroelectric device is needed to identify devices that meet or fail to meet required operational and lifetime characteristics. However, conventional testing mechanisms can be costly, time consuming, and destructive to the ferroelectric cells being tested.
Conventional testing mechanisms employ relatively high temperature and extended time bake cycles in order to simulate device life. The baking of memory arrays and/or devices as part of a test flow can potentially reduce the lifetime of the part, therefore, screening methods that include a thermal bake can also compromise the reliability of the memory device, even if the wares are not totally destroyed. Furthermore, conventional testing mechanisms can destroy the wafer upon which the devices are formed, thereby mitigating use on large numbers of wafers and/or devices.